The candidate will be part of newly developed team that will focus on verifying a complete FPGA-Based Prototype Solution for pre-silicon SW development. This new team will be exploring the challenge of FPGA Prototyping and HW-SW Co-Design and Verification, the candidate will learn a lot about FPGA Design and Verification world, FPGA Debugging challenges, FPGA Stimulus generation, FPGA Partitioning and all HW aspects of building the entire prototype flow.
• B. Sc. , M. Sc. in Electrical Engineering, Computer Engineering. Graduation Grade: Excellent or Very Good with Honor Degree.
• Good Knowledge about Digital/RTL Design Basics is required.
• Basic Knowledge about FPGA Flow, FPGA Design Challenges.
• Good knowledge about any of Hardware Description Languages such as VERILOG, VHDL or SystemVerilog is required.
• Candidate with Prior Knowledge of Mentor Graphics Tools such as Simulation, Synthesis, Design Entry or any Functional Verification Flows is a plus.
• Good knowledge with scripting languages such as Shell/Perl and TCL/TK is a plus.